The invention relates to the design and manufacture of integrated circuits. An integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, and wires, which are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer. Many phases of physical design may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language. An EDA system typically receives the high level behavior descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction using a computer synthesis process. A netlist describes interconnections of nodes and components on the chip and includes information on circuit primitives such as transistors and diodes, their sizes and interconnections, for example.
An integrated circuit designer may use a set of layout EDA application programs to create a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes. After an integrated circuit designer has created an initial integrated circuit layout, the integrated circuit designer then verifies and optimizes the integrated circuit layout using a set of EDA testing and analysis tools. Verification may include, for example, design rule checking to verify compliance with rules established for various IC parameters.
Prior to creating a physical layout for an RF circuit, the “front end” of the design process includes creating a schematic of the electrical design for simulation purposes. RF designers use transmission line components in the schematic to design topologies of the net. An RF net can be connected to multiple pins. RF designers specify how exactly the pin-to-pin connections go over the net by inserting transmission line components and specifying certain constraints of the transmission line components, such as the maximum/minimum pin-to-pin distance, pin-width, conductor spacing, topology, and the like.
If the simulation results are satisfactory, the topology is entered into a layout tool for creation of the physical layout of the RF circuit. Currently, there is no easy tool-assisted automated process to transfer routing intent directly from schematic to layout or to back-annotate layout changes upstream to the schematic. If a change in the design is necessary during layout (for example, if a width, length, or other such parameter needs to be adjusted), that change needs to be fed back into the schematic so that the design can be simulated again to be sure that the design will operate correctly if that change is incorporated into the design. In addition, parasitics generated during layout need to be fed back and simulated in the front end of the design process.
This process is iterated until the required topology behavior is achieved. Multiple iterations between schematic design, simulation and layout design are common practice to meet the design specification.
RF designs require a strong coupling between the logic and layout designer, since track routing of the layout has a strong impact on the design behavior. RFSiP designers specify the routing lengths and routing topology upfront in the schematic. Since there is no easy automated process for transferring this routing intent directly from schematic to layout, the designer manually shares the inputs regarding routing constraints and topology with the layout designer. Alternatively, the RF designer has to enter complicated properties on the schematic or a separate tool is used to capture topology which may not visually match with the schematic and is not intuitive to the layout designer. This situation is especially problematic for RF designs where the schematic captures an impedance matching circuit, so schematic sequence is very important.
In one approach for transferring topology from schematic to layout, transmission line topology is defined in the logic design using special transmission line components. These components map to shapes in the layout. Thus, the topology is transferred to the layout as a series of physical shapes having one-to-one mapping with the schematic. One problem with this approach is that the layout engineer loses routing flexibility since routing is exactly specified using components on the schematic itself. Another problem with this approach is that the logic schematic becomes complicated since the RF designer needs to add one schematic component per track shape. For example, the layout 100 shown in FIG. 1 would require three Microstrip and two bend component instances in the schematic.
In another approach for transferring topology from schematic to layout, no topology information is passed automatically from the simulation logic schematic to the layout. Rather, the topology is manually defined using separate signal exploration tools. For example, FIG. 2 depicts a signal exploration topology 200 for a single logical net in the schematic. Clearly, one problem with this approach is that there is no way to map the topology 200 shown in FIG. 2 back to the schematic. Another problem with this approach is that the schematic is non-intuitive to the layout designer, since it does not have any topology information. Still another problem with this approach is that topology violations cannot be detected in the schematic. This approach typically uses transmission line kind of components but in a separate UI.